1. Field of the Invention
The present invention relates to erasing methods of a nonvolatile memory cell and array using hot holes.
2. Description of the Prior Art
MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor, in which xe2x80x9cMetalxe2x80x9d is a representative of a conducting gate material) or SONOS (Silicon (as a conductive gate)-Oxide-Nitride-Oxide-Silicon) memories have been proposed for the improvement of MONOS (Metal-Nitride-Oxide-Semiconductor) memory in scaling down the thickness of the nitride film for the device scaling in the lateral dimension and scaling in the programming voltage and also for improvement in reproducibility. In the MONOS or SONOS memory (hereinafter xe2x80x9cMONOS memoryxe2x80x9d will be used to represent both), carrier trap sites, which are located in the nitride film and at the interface between the nitride and the top oxide, are used for capturing and storing carriers as electrical information.
In an original MONOS paper (Reference 1: E. Suzuki, et al., xe2x80x9cA Low-Voltage Alterable EEPROM with metal-oxide-nitride-oxide-semiconductor (MONOS) Structurexe2x80x9d, IEEE Transaction on Electron Devices, Vol. ED-30, February. 1983), direct tunneling of electrons and holes is used for the programming; that is, direct-tunnel injection of electrons into the trap sites is used for xe2x80x9cwritexe2x80x9d and direct-tunnel extraction of electrons from the trap sites and/or direct-tunnel injection of holes into the trap sites is used for xe2x80x9cerase.xe2x80x9d
On the other hand, injection of hot electrons into the trap sites for write and erasure by the injection of hot holes, which was originally applied to a floating gate device (see Reference 2: Y. Tarui, Y. Hayashi, K. Nagai, xe2x80x9cElectrically Reprogrammable Nonvolatile Memory,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol.SC-7, No.5, October., 1992, p.369-375), was proposed for programming single gate MONOS memories with thicker bottom oxide for better retention characteristics (see Reference 3: T.Y. Chan, K. K. Young, Chemning Hu, xe2x80x9cA True Single-Transistor Oxide-Nitride-Oxide EEPROM Devicexe2x80x9d, IEEE Electron Device Letters, Vol.EDL-8, No.3, 1987, p.93-95) and for doubling bit density (see Reference 4: B. Eitan, et al., xe2x80x9cCan NROM, a 2 Bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?xe2x80x9d, 1999 Conference on Solid State Devices and Materials, Tokyo, Extended Abstracts, p. 522-523, 1999).
The above single gate MONOS memory is characterized by a single gate bridging over a channel region where the single gate is disposed on ONO (oxide-nitride-oxide) gate insulator on the channel forming semiconductor region and on a part of the drain and source region.
For the xe2x80x9cwrite,xe2x80x9d hot electrons are injected into a part of the ONO gate insulator adjacent to a junction between the drain and the channel forming region and trapped in the trapping sites in the ONO gate insulator. For the xe2x80x9cerase,xe2x80x9d hot holes are injected into a part of the ONO gate insulator adjacent to the junction. However, erased states by hot holes turned out to be not reproducible and/or not stable with respect to the threshold voltage (Vth.) under certain hole injection bias conditions. In References 3 and 4, above, this instability was masked by stable electrical characteristics of a portion of the channel forming semiconductor region under an un-programmed portion of the ONO film because a portion of the channel forming semiconductor region under an erased portion of the ONO film is connected in series with the above xe2x80x9cunprogrammedxe2x80x9d portion of the channel forming semiconductor region, where Vth is higher than the Vth of the xe2x80x9cerasedxe2x80x9d portion. On the other hand, the instability will be observed if the majority of the un-programmed portion of the channel forming semiconductor region is controlled and turned on by a separate gate. In this case, another gate is laid side by side with and insulated from the separate gate disposed over the programmed portion of the channel forming semiconductor region.
It is a purpose of the present invention to provide a method of stably erasing a non-volatile memory in a gate insulator in which carrier-trapping sites for carrier storage are furnished.
It is another object of the present invention to provide a method of uniformly erasing a non-volatile memory array with a gate insulator in which carrier-trapping sites for carrier storage are furnished.
It is a further object of the invention to provide a method of erasing to realize better endurance of a non-volatile memory.
Accordingly, a first method of the present invention is the application of a discharge pulse(s) to a gate after erasure where the discharge pulse(s) discharges unstable holes injected into the gate insulator. Hot holes are injected into a gate insulator while negatively or zero biasing a conductive gate and positively biasing an opposite conductivity region whereby hot holes are generated in a surface of the opposite conductivity region, wherein positively biasing the opposite conductivity region with respect to a first channel forming semiconductor region is larger in value than an electric barrier height against the hot holes wherein the electric barrier is formed at an interface between the gate insulator and the opposite conductivity region. The conductive gate is positively biased to a voltage which generates an average electric field of more than 5 MV/cm in the first gate insulator.
A second method of the invention is injection of electrons into the trap sites of all the cells in a memory array to be erased before erasure. This makes Vth distribution across the memory array uniform after erasure. Electrons are injected into a gate insulator wherein the electrons are trapped in carrier trap sites within the gate insulator. Then, hot holes are injected into the gate insulator while applying a negative or zero bias to a conductive gate and applying a positive bias to an opposite conductivity region.
A third method of the invention is a reduced bias approach to erase stably the electrons stored in the trap sites. Hot holes are injected into a gate insulator while applying a negative or zero bias to a conductive gate and applying a positive bias to an opposite conductivity region wherein the positive bias is larger in value than an electric barrier height against the hot holes, wherein the electric barrier is formed at an interface between the gate insulator and the opposite conductivity region and wherein a sum of absolute values of the positive bias and ⅖ of the negative or zero bias is equal to or smaller than 6V wherein the negative or zero bias ranges from 0V to xe2x88x925V. This includes not only literally xe2x80x9cerase,xe2x80x9d but also xe2x80x9cannihilate or neutralizexe2x80x9d trapped electron charge by hole charge.
At least one of the above methods is applied to a memory cell or a memory array made from memory cells where the memory cell comprises at least:
a) a first channel forming semiconductor region in a surface of a substrate,
b) an opposite conductivity type region adjacent to the first channel forming semiconductor region and in the surface of the substrate,
c) a gate insulator on the first channel forming semiconductor region,
d) a conductive gate on the gate insulator and carrier trap sites in the gate insulator,
e) a second channel forming semiconductor region contacting the first channel forming semiconductor region in the surface of the substrate,
f) a second gate insulator on the second channel forming semiconductor region, and
g) a second gate on the second gate insulator where the second conducting gate is separated and insulated from the first conducting gate by an insulator.
More specifically, the memory cell comprises:
a) a channel forming semiconductor region of one conductivity type in a surface of a substrate where the substrate is a semiconductor substrate or a silicon-on-insulator (SOI) substrate,
b) a first opposite conductivity region and a second opposite conductivity region being disposed in the surface of the substrate where the first and second opposite conductivity regions are spaced apart and separated from each other by the channel forming semiconductor region,
c) the channel forming semiconductor region comprises:
i) a first channel-forming region laterally contacting the first opposite conductivity region,
ii) a second channel forming region contacting the second opposite conductivity region, and
iii) a third channel forming region in contact with the first and second channel forming regions and disposed between the first channel forming region and the second channel forming region,
d) gate insulators comprising:
i) a first gate insulator disposed on the first channel forming region and a part of the first opposite conductivity region adjacent to the first channel forming region,
ii) a second gate insulator disposed on the second channel forming region and a part of the second opposite conductivity region adjacent to the second channel forming region, and
iii) a third gate insulator disposed on the third channel forming region,
e) conductive gates comprising:
i) a first gate electrode on the first gate insulator,
ii) a second gate electrode on the second gate insulator, and
iii) a third gate electrode on the third gate insulator
wherein the gate electrodes are electrically insulated from each other and wherein a part of the first gate overlaps a part of the first opposite conductivity region via the first insulator and a part of the second gate overlaps a part of the second opposite conductivity region via the second insulator, and
f) carrier trapping sites for carrier storage furnished in the first and second insulators.
As one example, the carrier trapping sites are embedded in a three layered insulator structure. A typical embodiment is an oxide-nitride-oxide layer, where, in the fabrication process, carrier trapping sites are generated in the silicon nitride and/or in the interface between the silicon nitride and the silicon oxide. The silicon nitride can include a fraction of oxygen and the silicon oxide can be a nitrided oxide in which a part of the oxygen atoms of the oxide are replaced by nitrogen atoms.
As another example, the carrier trapping sites are realized by small particles of conductor or semiconductor such as silicon buried in the first and second gate insulators.